The Information Bottleneck for Soft Information in Flash Memory Read Channels
Semira Galijasevic
Abstract:
This paper applies the information bottleneck framework to the optimization of write voltage levels and read thresholds for the Flash memories. To enable low-latency, Flash memories have separate read channels for each bit stored a floating-gate transistor memory cell. This paper formulates the read threshold optimization problem as a series of information bottleneck problems, one for each bit stored in the cell. A greedy approach yields nearly optimal thresholds for any number of reads. This solution extends to handle the case of progressive reads, where the number of reads depends on the channel characteristics so that more reads are used for more severely degraded channels. This paper further expands its scope to explore how to design write voltage levels that maximize the lifetime of the Flash memory in the context of the optimized reads. Specifically, an iterative optimization of the support points is inspired by the dynamic assignment Blahut-Arimoto algorithm. This approach is used to identify the voltage levels that maximize the mutual information of the bit channel that provides the least mutual information.